{"id":4887,"date":"2023-07-14T16:53:53","date_gmt":"2023-07-14T08:53:53","guid":{"rendered":"https:\/\/inventec2.mjitec.tw\/?page_id=4887"},"modified":"2023-07-18T14:07:24","modified_gmt":"2023-07-18T06:07:24","slug":"configuration-through-optimization-for-in-memory-computing-hardware-and-simulators","status":"publish","type":"page","link":"https:\/\/inventec2.mjitec.tw\/zh-hans\/ai\/configuration-through-optimization-for-in-memory-computing-hardware-and-simulators\/","title":{"rendered":"Configuration through Optimization for In-Memory Computing Hardware and Simulators"},"content":{"rendered":"<div class=\"wpb-content-wrapper\"><p>[vc_row full_width=&#8221;stretch_row&#8221;][vc_column]<div id=\"rs-space-69e129da73875\" class=\"rs-space\">\r\n                <div class=\"rs-space-data\" data-conf=\"{&quot;uqid&quot;:&quot;69e129da73875&quot;,&quot;space_lg&quot;:&quot;150&quot;,&quot;space_md&quot;:&quot;80&quot;,&quot;space_sm&quot;:&quot;60&quot;,&quot;space_xs&quot;:&quot;60&quot;}\"><\/div>\t\t\t\r\n\t\t\t<\/div>[vc_row_inner el_class=&#8221;md-full-col&#8221;][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;1\/2&#8243;]\n        <div class=\"rs-heading    \">\n        \t<div class=\"title-inner\"  data-border-color=\"\">\n        \t\t\n\t            \n\t            <h2 class=\"title \" style=\"color: #333333\">Configuration through Optimization for In-Memory Computing Hardware and Simulators <\/h2>\n\t        <\/div><\/div>[vc_column_text css=&#8221;.vc_custom_1689324691501{margin-bottom: 20px !important;}&#8221;]<\/p>\n<div>\n<p>2022 IEEE International Workshop on Signal Processing Systems<\/p><\/div>\n<p>[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660542835761{margin-bottom: 5px !important;}&#8221;]<\/p>\n<div>\n<h6>\u4f5c\u8005<\/h6>\n<\/div>\n<p>[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1689324701050{margin-bottom: 20px !important;}&#8221;]<\/p>\n<div>\n<p>Ke-Han Li, Chih-Fan Hsu, Yu-Sheng Lin, Shao-Yi Chien, and Wei-Chao Chen<\/p><\/div>\n<p>[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1689324880852{margin-bottom: 5px !important;}&#8221;]<\/p>\n<div>\n<h6>\u53d1\u8868\u65e5\u671f<\/h6>\n<\/div>\n<p>[\/vc_column_text][vc_column_text]<\/p>\n<div>\n<p>Nov 2-4, 2022<\/p><\/div>\n<p>[\/vc_column_text][\/vc_column_inner][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;1\/2&#8243;][vc_single_image image=&#8221;5040&#8243; img_size=&#8221;full&#8221;][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column]<div id=\"rs-space-69e129da73b62\" class=\"rs-space\">\r\n                <div class=\"rs-space-data\" data-conf=\"{&quot;uqid&quot;:&quot;69e129da73b62&quot;,&quot;space_lg&quot;:&quot;150&quot;,&quot;space_md&quot;:&quot;80&quot;,&quot;space_sm&quot;:&quot;60&quot;,&quot;space_xs&quot;:&quot;60&quot;}\"><\/div>\t\t\t\r\n\t\t\t<\/div>[\/vc_column][\/vc_row][vc_row full_width=&#8221;stretch_row&#8221;][vc_column][vc_row_inner content_placement=&#8221;top&#8221; css=&#8221;.vc_custom_1657794580528{margin-bottom: 20px !important;}&#8221;][vc_column_inner el_class=&#8221;m_p paragraph_title&#8221; width=&#8221;1\/3&#8243;]\n        <div class=\"rs-heading   vc_custom_1657008747808  \">\n        \t<div class=\"title-inner\"  data-border-color=\"\">\n        \t\t\n\t            \n\t            <h2 class=\"title \" style=\"color: #333333\">\u6982\u8981 <\/h2>\n\t        <\/div><\/div>[\/vc_column_inner][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;2\/3&#8243;][vc_column_text]<span data-sheets-value=\"{&quot;1&quot;:2,&quot;2&quot;:&quot;In-Memory Computing (IMC) technologies are designed to reduce computing latency and improve energy efficiency by processing data in the memory. This attribute can greatly improve the efficiency of neural network training and inference. However, the output variance and the lack of input-output simulators hinder the adoption of IMC hardware in real products. In this paper, we aim to simulate unknown IMC hardware with existing simulators to reduce the development time for a new simulator. \\nBy assuming that the output behavior should be similar if the devices are similar, we formulate the hardware-simulator matching by the configuration optimization problem. Specifically, we design an optimization goal based on measuring the correlation coefficient between the summarized model outputs, per-class accuracy, running on the hardware and the simulator. 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This attribute can greatly improve the efficiency of neural network training and inference. However, the output variance and the lack of input-output simulators hinder the adoption of IMC hardware in real products. In this paper, we aim to simulate unknown IMC hardware with existing simulators to reduce the development time for a new simulator.<br \/>\nBy assuming that the output behavior should be similar if the devices are similar, we formulate the hardware-simulator matching by the configuration optimization problem. Specifically, we design an optimization goal based on measuring the correlation coefficient between the summarized model outputs, per-class accuracy, running on the hardware and the simulator. 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