{"id":4058,"date":"2022-07-15T16:40:43","date_gmt":"2022-07-15T08:40:43","guid":{"rendered":"https:\/\/inventec2.mjitec.tw\/?page_id=4058"},"modified":"2023-07-18T14:07:25","modified_gmt":"2023-07-18T06:07:25","slug":"gratetile","status":"publish","type":"page","link":"https:\/\/inventec2.mjitec.tw\/zh-hans\/ai\/gratetile\/","title":{"rendered":"GrateTile"},"content":{"rendered":"

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GrateTile: Efficient Sparse Tensor Tiling for CNN Processing <\/h2>\n\t <\/div><\/div>[vc_column_text css=”.vc_custom_1660543620218{margin-bottom: 20px !important;}”]<\/p>\n
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IEEE Workshop on Signal Processing Systems (SiPS)<\/p>\n<\/div>\n

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Yu-Sheng Lin, Hung Chang Lu, Yang-Bin Tsao, Yi-Min Chih, Wei-Chao Chen, Shao-Yi Chien<\/p>\n<\/div>\n

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Sep-20<\/p>\n<\/div>\n

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\u6982\u8981 <\/h2>\n\t <\/div><\/div>[\/vc_column_inner][vc_column_inner el_class=”m_p” width=”2\/3″][vc_column_text]We propose GrateTile, an efficient, hardware friendly data storage scheme for sparse CNN feature maps (activations). It divides data into uneven-sized subtensors and, with small indexing overhead, stores them in a compressed yet randomly accessible format. This design enables modern CNN accelerators to fetch and decompressed sub-tensors on-the-fly in a tiled processing manner.<\/p>\n

GrateTile is suitable for architectures that favor aligned, coalesced data access, and only requires minimal changes to the overall architectural design. We simulate GrateTile with state-of-the-art CNNs and show an average of 55% DRAM bandwidth reduction while using only 0.6% of feature map size for indexing storage.[\/vc_column_text][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column]

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