{"id":4247,"date":"2022-07-15T16:17:53","date_gmt":"2022-07-15T08:17:53","guid":{"rendered":"https:\/\/inventec2.mjitec.tw\/?page_id=4247"},"modified":"2024-01-17T11:17:00","modified_gmt":"2024-01-17T03:17:00","slug":"merit","status":"publish","type":"page","link":"https:\/\/inventec2.mjitec.tw\/en\/ai\/merit\/","title":{"rendered":"MERIT"},"content":{"rendered":"<div class=\"wpb-content-wrapper\"><p>[vc_row full_width=&#8221;stretch_row&#8221;][vc_column]<div id=\"rs-space-69e10d03e8fb1\" class=\"rs-space\">\r\n                <div class=\"rs-space-data\" data-conf=\"{&quot;uqid&quot;:&quot;69e10d03e8fb1&quot;,&quot;space_lg&quot;:&quot;150&quot;,&quot;space_md&quot;:&quot;80&quot;,&quot;space_sm&quot;:&quot;60&quot;,&quot;space_xs&quot;:&quot;60&quot;}\"><\/div>\t\t\t\r\n\t\t\t<\/div>[vc_row_inner el_class=&#8221;md-full-col&#8221;][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;1\/2&#8243;]\n        <div class=\"rs-heading    \">\n        \t<div class=\"title-inner\"  data-border-color=\"\">\n        \t\t\n\t            \n\t            <h2 class=\"title \" style=\"color: #333333\">MERIT: Tensor transform for memory-efficient vision processing on parallel architectures <\/h2>\n\t        <\/div><\/div>[vc_column_text css=&#8221;.vc_custom_1660542471959{margin-bottom: 20px !important;}&#8221;]<\/p>\n<div>\n<p>IEEE Transactions on Very Large Scale Integration Systems 2019<\/p>\n<\/div>\n<p>[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660547617964{margin-bottom: 5px !important;}&#8221;]<\/p>\n<div>\n<h6>Authors<\/h6>\n<\/div>\n<p>[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660542486676{margin-bottom: 20px !important;}&#8221;]<\/p>\n<div>\n<p>Yu-Sheng Lin, Wei-Chao Chen, Shao-Yi Chien<\/p>\n<\/div>\n<p>[\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660547628068{margin-bottom: 5px !important;}&#8221;]<\/p>\n<div>\n<h6>Published<\/h6>\n<\/div>\n<p>[\/vc_column_text][vc_column_text]<\/p>\n<div>\n<p>2019\/12\/6<\/p>\n<\/div>\n<p>[\/vc_column_text][\/vc_column_inner][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;1\/2&#8243;][vc_single_image image=&#8221;2518&#8243; img_size=&#8221;full&#8221;][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column]<div id=\"rs-space-69e10d03e90be\" class=\"rs-space\">\r\n                <div class=\"rs-space-data\" data-conf=\"{&quot;uqid&quot;:&quot;69e10d03e90be&quot;,&quot;space_lg&quot;:&quot;150&quot;,&quot;space_md&quot;:&quot;80&quot;,&quot;space_sm&quot;:&quot;60&quot;,&quot;space_xs&quot;:&quot;60&quot;}\"><\/div>\t\t\t\r\n\t\t\t<\/div>[\/vc_column][\/vc_row][vc_row full_width=&#8221;stretch_row&#8221;][vc_column][vc_row_inner content_placement=&#8221;top&#8221; css=&#8221;.vc_custom_1657794580528{margin-bottom: 20px !important;}&#8221;][vc_column_inner el_class=&#8221;m_p paragraph_title&#8221; width=&#8221;1\/3&#8243;]\n        <div class=\"rs-heading   vc_custom_1660547641053  \">\n        \t<div class=\"title-inner\"  data-border-color=\"\">\n        \t\t\n\t            \n\t            <h2 class=\"title \" style=\"color: #333333\">Abstract <\/h2>\n\t        <\/div><\/div>[\/vc_column_inner][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;2\/3&#8243;][vc_column_text]We propose a mathematical formulation which can be useful for transferring the parallel algorithm optimization knowledge across computing platforms. We discover that data movement and storage inside parallel processor architectures can be viewed as tensor transforms across memory hierarchies, making it possible to describe many memory optimization techniques mathematically. Such transform, which we call Memory Efficient Ranged Inner-Product Tensor (MERIT) transform, can be applied to not only DNN tasks but also many traditional machine learning and computer vision computations.<\/p>\n<p>We also demonstrate that many popular applications can be converted to a succinct MERIT notation on GPUs, speeding up GPU kernels up to 20 times while using only half as many code tokens. We also use the principle of the proposed transform to design a specialized hardware unit called MERIT-z processor. This processor can be applied to a variety of DNN tasks as well as other computer vision tasks while providing comparable area and power efficiency to dedicated DNN ASICs.[\/vc_column_text][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column]<div id=\"rs-space-69e10d03e917c\" class=\"rs-space\">\r\n                <div class=\"rs-space-data\" data-conf=\"{&quot;uqid&quot;:&quot;69e10d03e917c&quot;,&quot;space_lg&quot;:&quot;80&quot;,&quot;space_md&quot;:&quot;80&quot;,&quot;space_sm&quot;:&quot;60&quot;,&quot;space_xs&quot;:&quot;60&quot;}\"><\/div>\t\t\t\r\n\t\t\t<\/div>[\/vc_column][\/vc_row][vc_row][vc_column width=&#8221;1\/3&#8243; el_class=&#8221;m_p keyword_title&#8221;][vc_column_text]<\/p>\n<h2>Keywords<\/h2>\n<p>[\/vc_column_text][\/vc_column][vc_column width=&#8221;2\/3&#8243; el_class=&#8221;m_p keyword&#8221;][vc_row_inner content_placement=&#8221;middle&#8221;][vc_column_inner width=&#8221;1\/3&#8243;][vc_raw_html]JTNDdWwlMjBjbGFzcyUzRCUyMnN0eWxlbGlzdGluZyUyMiUzRSUwQSUyMCUwOSUzQ2xpJTIwc3R5bGUlM0QlMjJsaW5lLWhlaWdodCUzQTM0cHglM0IlMjIlM0VETk4lMjBBY2NlbGVyYXRvciUzQyUyRmxpJTNFJTBBJTNDJTJGdWwlM0U=[\/vc_raw_html][\/vc_column_inner][vc_column_inner width=&#8221;1\/3&#8243;][vc_raw_html]JTNDdWwlMjBjbGFzcyUzRCUyMnN0eWxlbGlzdGluZyUyMiUzRSUwQSUyMCUwOSUwQSUzQyUyRnVsJTNF[\/vc_raw_html][\/vc_column_inner][vc_column_inner width=&#8221;1\/3&#8243;][vc_raw_html]JTNDdWwlMjBjbGFzcyUzRCUyMnN0eWxlbGlzdGluZyUyMiUzRSUwQSUyMCUwOSUwQSUzQyUyRnVsJTNF[\/vc_raw_html][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column]<div id=\"rs-space-69e10d03e91bc\" class=\"rs-space\">\r\n                <div class=\"rs-space-data\" data-conf=\"{&quot;uqid&quot;:&quot;69e10d03e91bc&quot;,&quot;space_lg&quot;:&quot;80&quot;,&quot;space_md&quot;:&quot;80&quot;,&quot;space_sm&quot;:&quot;60&quot;,&quot;space_xs&quot;:&quot;60&quot;}\"><\/div>\t\t\t\r\n\t\t\t<\/div>[\/vc_column][\/vc_row][vc_row full_width=&#8221;stretch_row&#8221; el_class=&#8221;bg&#8221; css=&#8221;.vc_custom_1657248474326{padding-top: 50px !important;padding-bottom: 50px !important;}&#8221;][vc_column][vc_column_text css=&#8221;.vc_custom_1660547685983{margin-bottom: 20px !important;}&#8221;]<\/p>\n<h3 style=\"text-align: center; color: #fff;\">Download<\/h3>\n<p>[\/vc_column_text][vc_row_inner content_placement=&#8221;middle&#8221;][vc_column_inner el_class=&#8221;download_btn_wrap&#8221;][vc_btn title=&#8221;PDF&#8221; style=&#8221;flat&#8221; color=&#8221;white&#8221; align=&#8221;center&#8221; link=&#8221;url:https%3A%2F%2Farxiv.org%2Fpdf%2F1911.03458.pdf|target:_blank&#8221; el_class=&#8221;download_btn&#8221;][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row]<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>[vc_row full_width=&#8221;stretch_row&#8221;][vc_column][vc_row_inner el_class=&#8221;md-full-col&#8221;][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;1\/2&#8243;][vc_column_text css=&#8221;.vc_custom_1660542471959{margin-bottom: 20px !important;}&#8221;] IEEE Transactions on Very Large Scale Integration Systems 2019 [\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660547617964{margin-bottom: 5px !important;}&#8221;] Authors [\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660542486676{margin-bottom: 20px !important;}&#8221;] Yu-Sheng Lin, Wei-Chao Chen, Shao-Yi Chien [\/vc_column_text][vc_column_text css=&#8221;.vc_custom_1660547628068{margin-bottom: 5px !important;}&#8221;] Published [\/vc_column_text][vc_column_text] 2019\/12\/6 [\/vc_column_text][\/vc_column_inner][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;1\/2&#8243;][vc_single_image image=&#8221;2518&#8243; img_size=&#8221;full&#8221;][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column][\/vc_column][\/vc_row][vc_row full_width=&#8221;stretch_row&#8221;][vc_column][vc_row_inner content_placement=&#8221;top&#8221; css=&#8221;.vc_custom_1657794580528{margin-bottom: 20px !important;}&#8221;][vc_column_inner el_class=&#8221;m_p paragraph_title&#8221; width=&#8221;1\/3&#8243;][\/vc_column_inner][vc_column_inner el_class=&#8221;m_p&#8221; width=&#8221;2\/3&#8243;][vc_column_text]We propose&#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":4975,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-4247","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages\/4247","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/comments?post=4247"}],"version-history":[{"count":0,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages\/4247\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages\/4975"}],"wp:attachment":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/media?parent=4247"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}