{"id":4244,"date":"2022-07-15T16:40:43","date_gmt":"2022-07-15T08:40:43","guid":{"rendered":"https:\/\/inventec2.mjitec.tw\/?page_id=4244"},"modified":"2024-01-17T11:15:32","modified_gmt":"2024-01-17T03:15:32","slug":"gratetile","status":"publish","type":"page","link":"https:\/\/inventec2.mjitec.tw\/en\/ai\/gratetile\/","title":{"rendered":"GrateTile"},"content":{"rendered":"

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GrateTile: Efficient Sparse Tensor Tiling for CNN Processing <\/h2>\n\t <\/div><\/div>[vc_column_text css=”.vc_custom_1660542556927{margin-bottom: 20px !important;}”]<\/p>\n
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IEEE Workshop on Signal Processing Systems (SiPS)<\/p>\n<\/div>\n

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Authors<\/h6>\n<\/div>\n

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Yu-Sheng Lin, Hung Chang Lu, Yang-Bin Tsao, Yi-Min Chih, Wei-Chao Chen, Shao-Yi Chien<\/p>\n<\/div>\n

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Published<\/h6>\n<\/div>\n

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2020\/9\/23<\/p>\n<\/div>\n

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Abstract <\/h2>\n\t <\/div><\/div>[\/vc_column_inner][vc_column_inner el_class=”m_p” width=”2\/3″][vc_column_text]We propose GrateTile, an efficient, hardware friendly data storage scheme for sparse CNN feature maps (activations). It divides data into uneven-sized subtensors and, with small indexing overhead, stores them in a compressed yet randomly accessible format. This design enables modern CNN accelerators to fetch and decompressed sub-tensors on-the-fly in a tiled processing manner.<\/p>\n

GrateTile is suitable for architectures that favor aligned, coalesced data access, and only requires minimal changes to the overall architectural design. We simulate GrateTile with state-of-the-art CNNs and show an average of 55% DRAM bandwidth reduction while using only 0.6% of feature map size for indexing storage.[\/vc_column_text][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column]

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Keywords<\/h2>\n

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Download<\/h3>\n

[\/vc_column_text][vc_row_inner content_placement=”middle”][vc_column_inner el_class=”download_btn_wrap”][vc_btn title=”PDF” style=”flat” color=”white” align=”center” link=”url:https%3A%2F%2Farxiv.org%2Fpdf%2F2009.08685.pdf|target:_blank” el_class=”download_btn”][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row]<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"

[vc_row full_width=”stretch_row”][vc_column][vc_row_inner el_class=”md-full-col”][vc_column_inner el_class=”m_p” width=”1\/2″][vc_column_text css=”.vc_custom_1660542556927{margin-bottom: 20px !important;}”] IEEE Workshop on Signal Processing Systems (SiPS) [\/vc_column_text][vc_column_text css=”.vc_custom_1660547387771{margin-bottom: 5px !important;}”] Authors [\/vc_column_text][vc_column_text css=”.vc_custom_1660542573327{margin-bottom: 20px !important;}”] Yu-Sheng Lin, Hung Chang Lu, Yang-Bin Tsao, Yi-Min Chih, Wei-Chao Chen, Shao-Yi Chien [\/vc_column_text][vc_column_text css=”.vc_custom_1660547399021{margin-bottom: 5px !important;}”] Published [\/vc_column_text][vc_column_text] 2020\/9\/23 [\/vc_column_text][\/vc_column_inner][vc_column_inner el_class=”m_p” width=”1\/2″][vc_single_image image=”2513″ img_size=”full”][\/vc_column_inner][\/vc_row_inner][\/vc_column][\/vc_row][vc_row][vc_column][\/vc_column][\/vc_row][vc_row full_width=”stretch_row”][vc_column][vc_row_inner content_placement=”top” css=”.vc_custom_1657794580528{margin-bottom: 20px !important;}”][vc_column_inner el_class=”m_p…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":4975,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-4244","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages\/4244","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/comments?post=4244"}],"version-history":[{"count":0,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages\/4244\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/pages\/4975"}],"wp:attachment":[{"href":"https:\/\/inventec2.mjitec.tw\/en\/wp-json\/wp\/v2\/media?parent=4244"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}